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? 2006 microchip technology inc. ds21490c-page 1 tcn75 features: ? solid-state temperature sensing: 0.5c accuracy (typ.) ? operates from -55c to +125c ? operating supply range: 2.7v to 5.5v ? programmable trip point and hysteresis with power-up defaults ? standard 2-wire serial interface ? thermal event alarm output functions as interrupt or comparator/thermostat output ? up to 8 tcn75s may share the same bus ? shutdown mode for low standby power consumption ? 5v tolerant i/o at v dd = 3v ?low power: - 250 a (typ.) operating -1 a (typ.) shutdown mode ? 8-pin soic and msop packaging applications: ? thermal protection for high-performance cpus ? solid-state thermometer ? fire/heat alarms ? thermal management in electronic systems: - computers - telecom racks - power supplies/ups/amplifiers ? copiers/office electronics ? consumer electronics ? process control package type general description: the tcn75 is a serially programmable temperature sensor that notifies the host controller when ambient temperature exceeds a user programmed set point. hysteresis is also programmable. the int/cmptr output is programmable as either a simple comparator for thermostat operation or as a temperature event interrupt. communication with the tcn75 is accomplished via a two-wire bus that is compatible with industry standard protocols. this permits reading the current temperature, programming the set point and hysteresis, and configuring the device. the tcn75 powers up in comparator mode with a default set point of 80c with 5c hysteresis. defaults allow independent operation as a stand-alone thermostat. a shutdown command may be sent via the 2-wire bus to activate the low-power standby mode. address selection inputs allow up to eight tcn75s to share the same 2-wire bus for multizone monitoring. all registers can be read by the host and the int/ cmptr output?s polarity is user programmable. both polled and interrupt driven systems are easily accommodated. small physical size, low installed cost, and ease-of-use make the tcn75 an ideal choice for implementing sophisticated system management schemes. 1 2 3 4 8 7 6 5 tcn75moa 1 2 3 4 8 7 6 5 tcn75mua a1 a0 a2 soic msop scl int/cmptr gnd sda scl int/cmptr gnd sda v dd a1 a0 a2 v dd 2-wire serial temperature sensor and thermal monitor
tcn75 ds21490c-page 2 ? 2006 microchip technology inc. device selection table functional block diagram part number supply voltage package junction temperature range tcn75-3.3moa 3.3 8-pin soic -55c to +125c tcn75-5.0moa 5.0 8-pin soic -55c to +125c tcn75-3.3mua 3.3 8-pin msop -55c to +125c tcn75-5.0mua 5.0 8-pin msop -55c to +125c control logic tcn75 int/cmptr register set t set t hyst configuration a 0 v dd temp sensor scl sda a 1 a 2 temperature 9-bit ds a/d converter two wire serial port interface
? 2006 microchip technology inc. ds21490c-page 3 tcn75 1.0 electrical characteristics absolute maximum ratings* supply voltage (v dd ) ............................................ 6.0v esd susceptibility (note 3) ............................... 1000v voltage on pins: a0, a1, a2 .......... (gnd ? 0.3v) to (v dd + 0.3v) voltage on pins: sda, scl, int/cmptr .. (gnd ? 0.3v) to 5.5v thermal resistance (junction to ambient) 8-pin soic.......................................... 170c/w 8-pin msop ....................................... 250c//w operating temperature range (t j ): -55c to +125c storage temperature range (t stg ): -65c to +150c *stresses above those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only and functional operation of the device at these or any other conditions above those indicated in the operation sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. tcn75 electrical specifications electrical characteristics: v dd = 2.7v ? 5.5v, -55c (t a = t j ) 125c, unless otherwise noted. symbol parameter min typ max units test conditions power supply v dd power supply voltage 2.7 ? 5.5 ? i dd operating current ? ? 0.250 ? ? 1.0 ma serial port inactive (t a = t j = 25c) serial port active i dd1 standby supply current ? 1 ? a shutdown mode, serial port inactive (t a = t j = 25c) int/cmptr output i ol sink current: int/cmptr, sda outputs ?14ma note 1 t trip int/cmptr response time 1 ? 6 t conv user programmable v ol output low voltage ? ? 0.8 v i ol = 4.0 ma temp-to-bits converter t temperature accuracy (note 2) ?3? c -55c t a +125c v dd = 3.3v: tcn75-3.3 moa, tcn75-3.3 mua v dd = 5.0v: tcn75-5.0 moa, tcn75-5.0 mua ?0.53 c25c t a 100c t conv conversion time ? 55 ? msec t set(pu) temp default value ? 80 ? c power-up t hyst(pu) t hyst default value ? 75 ? c power-up 2-wire serial bus interface v ih logic input high v dd x 0.7 ? ? v v il logic input low ? ? v dd x 0.3 v v ol logic output low ? ? 0.4 v i ol = 3 ma c in input capacitance sda, scl ? 15 ? pf i leak i/o leakage ? 100 ? pa (t a = t j = 25c) i ol(sda) sda output low current ? ? 6 ma
tcn75 ds21490c-page 4 ? 2006 microchip technology inc. timing diagram tcn75 electrical specifications (continued) electrical characteristics: 2.7v v dd 5.5v; -55c (t a = t j ) 125c, c l = 80 pf, unless otherwise noted. symbol parameter min typ max unit test conditions serial port timing f sc serial port frequency 0 100 400 khz t low low clock period 1250 ? ? nsec t high high clock period 1250 ? ? nsec t r scl and sda rise time ? ? 250 nsec t f scl and sda fall time ? ? 250 nsec t su(start) start condition setup time (for repeated start condition) 1250 ? ? nsec t sc scl clock period 2.5 ? ? sec t h(start) start condition hold time 100 ? ? nsec t dsu data in setup time to scl high 100 ? ? nsec t dh data in hold time after scl low 0 ? ? nsec t su(stop) stop condition setup time 100 ? ? nsec t idle bus free time prior to new transition 1250 ? ? nsec note 1: output current should be minimized for best temperature accuracy. power dissipation within the tcn75 will cause self-heating an d temperature drift. at maximum rated output current and saturation voltage, 4 ma and 0.8v, respectively, the error amounts to 0. 544c for the soic. 2: all part types of the tcn75 will operate properly over the wider power supply range of 2.7v to 5.5v. each part type is tested a nd specified for rated accuracy at its nominal supply voltage. as v dd varies from the nominal value, accuracy will degrade 1c/v of v dd change. 3: human body model, 100 pf discharged through a 1.5k resistor. scl t sc t dsu t su (stop) t h (start) t dh sda data in sda data out
? 2006 microchip technology inc. ds21490c-page 5 tcn75 2.0 pin descriptions the descriptions of the pins are listed in table 2-1. table 2-1: pin function table pin number (8-pin soic) 8-pin msop) symbol description 1 sda bidirectional serial data. 2 scl serial data clock input. 3 int/cmptr interrupt or comparator output. 4 gnd system ground. 5a 2 address select pin (msb). 6a 1 address select pin. 7a 0 address select pin (lsb). 8v dd power supply input.
tcn75 ds21490c-page 6 ? 2006 microchip technology inc. 3.0 detailed description a typical tcn75 hardware connection is shown in figure 3-1. figure 3-1: typical application 3.1 serial data (sda) bidirectional. serial data is transferred in both directions using this pin. 3.2 serial clock (scl) input. clocks data into and out of the tcn75. 3.3 int/cmptr open collector, programmable polarity. in comparator mode, unconditionally driven active any time temperature exceeds the value programmed into the t set register. int/cmptr will become inactive when temperature subsequently falls below the t hyst set- ting. (see section 5.0 ?register set and program- mer?s model? , register set and programmer?s model). in interrupt mode, int/cmptr is also made active by temp exceeding t set ; it is unconditionally reset to its inactive state by reading any register via the 2-wire bus. if and when temperature falls below t hyst , int/cmptr is again driven active. reading any regis- ter will clear the t hyst interrupt. in interrupt mode, the int/cmptr output is unconditionally reset upon enter- ing shutdown mode. if programmed as an active-low output, it can be wire-ored with any number of other open collector devices. most systems will require a pull-up resistor for this configuration. note that current sourced from the pull-up resistor causes power dissipation and may cause internal heat- ing of the tcn75. to avoid affecting the accuracy of ambient temperature readings, the pull-up resistor should be made as large as possible. int/cmptr?s output polarity may be programmed by writing to the int/cmptr polarity bit in the config register. the default is active low. 3.4 address (a2, a1, a0) inputs. sets the three least significant bits of the tcn75 8-bit address. a match between the tcn75?s address and the address specified in the serial bit stream must be made to initiate communication with the tcn75. many protocol-compatible devices with other addresses may share the same 2-wire bus. 3.5 slave address the four most significant bits of the address byte (a6, a5, a4, a3) are fixed to 1001[b]. the states of a2, a1 and a0 in the serial bit stream must match the states of the a2, a1 and a0 address inputs for the tcn75 to respond with an acknowledge (indicating the tcn75 is on the bus and ready to accept data). the slave address is represented in table 3-1. a 0 a 1 a 2 sda scl +v dd (3v to 5.5v) address (set as desired) i 2 c ? interface c bypass to controller 0.1 f recommended unless device is mounted close to cpu int/cmptr 7 6 5 1 2 3 8 4 tcn75 table 3-1: tcn75 slave address 1 0 0 1 a2 a1 a0 msb lsbs
? 2006 microchip technology inc. ds21490c-page 7 tcn75 3.6 comparator/interrupt modes int/cmptr behaves differently depending on whether the tcn75 is in comparator mode or interrupt mode. comparator mode is designed for simple thermostatic operation. int/cmptr will go active anytime temp exceeds t set . when in comparator mode, int/ cmptr will remain active until temp falls below t hyst , whereupon it will reset to its inactive state. the state of int/cmptr is maintained in shutdown mode when the tcn75 is in comparator mode. in interrupt mode, int/cmptr will remain active indefinitely, even if temp falls below t hyst , until any register is read via the 2-wire bus. interrupt mode is better suited to inter- rupt driven microprocessor-based systems. the int/ cmptr output may be wire-or?ed with other interrupt sources in such systems. note that a pull-up resistor is necessary on this pin since it is an open-drain output. entering shutdown mode will unconditionally reset int/ cmptr when in interrupt mode.
tcn75 ds21490c-page 8 ? 2006 microchip technology inc. 4.0 shutdown mode when the appropriate bit is set in the configuration reg- ister (config) the tcn75 enters its low-power shut- down mode (i dd = 1 a, typical) and the temperature- to-digital conversion process is halted. the tcn75?s bus interface remains active and temp, t set , and t hyst may be read from and written to. transitions on sda or scl due to external bus activity may increase the standby power consumption. if the tcn75 is in interrupt mode, the state of int/cmptr will be reset upon entering shutdown mode. 4.1 fault queue to lessen the probability of spurious activation of int/ cmptr the tcn75 may be programmed to filter out transient events. this is done by programming the desired value into the fault queue. logic inside the tcn75 will prevent the device from triggering int/ cmptr unless the programmed number of sequential temperature-to-digital conversions yield the same qualitative result. in other words, the value reported in temp must remain above t set or below t hyst for the consecutive number of cycles programmed in the fault queue. up to a six-cycle ?filter? may be selected. see section 5.0 ?register set and programmer?s model? , register set and programmer?s model. 4.2 serial port operation the serial clock input (scl) and bidirectional data port (sda) form a 2-wire bidirectional serial port for pro- gramming and interrogating the tcn75. the following table indicates tcn75 conventions that are used in this bus scheme. table 4-1: serial bus conventions all transfers take place under control of a host, usually a cpu or microcontroller, acting as the master, which provides the clock signal for all transfers. the tcn75 always operates as a slave. this serial protocol is illustrated in figure 5-1. all data transfers have two phases; and all bytes are transferred msb first. accesses are initiated by a start condition, followed by a device address byte and one or more data bytes. the device address byte includes a read/write selection bit. each access must be terminated by a stop condi- tion. a convention called acknowledge (ack) confirms receipt of each byte. note that sda can change only during periods when scl is low (sda changes while scl is high are reserved for start and stop condi- tions). 4.3 start condition (start) the tcn75 continuously monitors the sda and scl lines for a start condition (a high-to-low transition of sda while scl is high), and will not respond until this condition is met. term explanation transmitter the device sending data to the bus. receiver the device receiving data from the bus. master the device which controls the bus: initiating transfers (start), generating the clock, and terminating transfers (stop). slave the device addressed by the master. start a unique condition signaling the beginning of a transfer indicated by sda falling (high ? low) while scl is high. stop a unique condition signaling the end of a transfer indicated by sda rising (low ? high) while scl is high. ack a receiver acknowledges the receipt of each byte with this unique condition. the receiver drives sda low during scl high of the ack clock-pulse. the master provides the clock pulse for the ack cycle. not busy when the bus is idle, both sda & scl will remain high. data valid the state of sda must remain stable during the high period of scl in order for a data bit to be considered valid. sda only changes state while scl is low during normal data transfers. (see start and stop conditions).
? 2006 microchip technology inc. ds21490c-page 9 tcn75 4.3.1 address byte immediately following the start condition, the host must next transmit the address byte to the tcn75. the four most significant bits of the address byte (a6, a5, a4, a3) are fixed to 1001(b). the states of a2, a1 and a0 in the serial bit stream must match the states of the a2, a1 and a0 address inputs for the tcn75 to respond with an acknowledge (indicating the tcn75 is on the bus and ready to accept data). the eighth bit in the address byte is a read/write bit. this bit is a ? 1 ? for a read operation or ? 0 ? for a write operation. 4.3.2 acknowledge (ack) acknowledge (ack) provides a positive handshake between the host and the tcn75. the host releases sda after transmitting eight bits then generates a ninth clock cycle to allow the tcn75 to pull the sda line low to acknowledge that it successfully received the previous eight bits of data or address. 4.3.3 data byte after a successful ack of the address byte, the host must next transmit the data byte to be written or clock out the data to be read. (see the appropriate timing diagrams.) ack will be generated after a successful write of a data byte into the tcn75. 4.3.4 stop condition (stop) communications must be terminated by a stop condition (a low-to-high transition of sda while scl is high). the stop condition must be communicated by the transmitter to the tcn75. 4.3.5 power supply to minimize temperature measurement error, the tcn75-3.3 moa and tcn75-3.3 mua are factory cal- ibrated at a supply voltage of 3.3v 5% and the tcn75-5.0 moa and tcn75-5.0 mua are factory cal- ibrated at a supply voltage of 5v 5%. either device is fully operational over the power supply voltage range of 2.7v to 5.5v, but with a lower measurement accuracy. the typical value of this power supply-related error is 2c.
tcn75 ds21490c-page 10 ? 2006 microchip technology inc. 5.0 register set and programmer?s model table 5-2: configuration register (config), 8 bits, read/ write d0: shutdown: 0 = normal operation 1 = shutdown mode d1: cmptr/int: 0 = comparator mode 1 = interrupt mode d2: int/cmptr polarity: 0 = active low 1 = active high d3 ? d4: fault queue: number of sequential temperature-to-digital conversions with the same result before the int/cmptr output is updated: table 5-1: register (point), 8 bits, write only d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] must be set to zero pointer register selection via the pointer register d1 d0 register selection 00 temp 01 config 10 t hyst 11 t set d [7] d [6] d [5] d [4] d [3] d [2] d [1] d [0] must be set to z e r o fault queue int/ cmptr, polarity com p/int shut- down d4 d3 number of conversions 00 1 (power-up default) 01 2 10 4 11 6
? 2006 microchip technology inc. ds21490c-page 11 tcn75 table 5-3: temperature (temp) register, 16 bits, read only the binary value in this register represents ambient temperature following a conversion cycle. table 5-4: temperature set point (t set ) register, 16 bits, read/write table 5-5: hysteresis (t hyst ) register, 16 bits, read/write in the temp, t set , and t hyst registers, each unit value represents one-half degree (celsius). the value is in 2?s ? complement binary format such that a read- ing of 000000000b corresponds to 0c. examples of this temperature to binary value relationship are shown in table 5-6. table 5-6: temperature to digital value conversion table 5-7: tcn75?s register set summary d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] msb d7 d6 d5 d4 d3 d2 d1 lsb xxxxx x x d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] msb d7 d6 d5 d4 d3 d2 d1 lsb xxxxx x x d[15] d[14] d[13] d[12] d[11] d[10] d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] d[0] msb d7 d6 d5 d4 d3 d2 d1 lsb xxxxx x x temperature binary value hex value +125c 0 11111010 0fa +25c 0 00110010 032 +0.5c 0 00000001 001 0c 0 00000000 00 0.5c 1 11111111 1ff -25c 1 11001110 1ce -40c 1 10110000 1b0 -55c 1 10010010 192 name description width read write notes temp ambient temperature 16 x 2?s complement format tset temperature setpoint 16 xx 2?s complement format t hyst temperature hysteresis 16 xx 2?s complement format point register pointer 8 xx config configuration register 8 xx
tcn75 ds21490c-page 12 ? 2006 microchip technology inc. figure 5-1: timing diagrams 1 1 start by master ack by tcn75 address byte (a) typical 2-byte read from preset pointer location such as temp, t os , t hyst (b) typical pointer set followed by immediate read for 2-byte register such as temp, t os , t hyst ack by master most significant data byte stop cond by master no ack by master least significant data byte d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1a2a1a0 r/w 00 1 91 99 1 1 start by master ack by tcn75 address byte ack by tcn75 pointer byte 000000 d1 d0 . . . . . . . . . . 1 a2 a1 a0 r/w 00 1 99 1 1 start by master ack by tcn75t address byte (c) typical 1-byte read from configuration register with preset pointer data byte stop cond by master no ack by master d7 d6 d5 d4 d3 d2 d1 d0 1 a2 a1 a0 r/w 00 1 99 1 1 repeat start by master ack by tcn75 address byte ack by master most significant data byte stop cond by master no ack by master least significant data byte d7 d6 d5 d4 d3 d2 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 1 a2 a1 a0 r/w 00 1 91 99
? 2006 microchip technology inc. ds21490c-page 13 tcn75 timing diagrams (continued) 1 1 start by master ack by tcn75 address byte (d) typical pointer set followed by immediate read from configuration register ack by tcn75 repeat start by master pointer byte ack by tcn75 stop cond by master no ack by master address byte 0000000 d0 d7 d6 d5 d4 d3 d2 d1 d0 100 a2 1 a1 a0 1 a2 a1 a0 r/w 00 1 91 99 19 r/w data byte 1 1 start by master ack by tcn75 address byte (f) t os and t hyst write ack by tcn75 pointer byte ack by tcn75 stop cond by master ack by tcn75 most significant data byte 000000 d1 d0 d7 d6 d5 d4 d3 d2 d1 d0 d6 d5 d4 d2 d3 d1 d0 1 a2 a1 a0 r/w 00 1 91 99 19 d7 least significant data byte 1 1 start by master ack by tcn75t address byte (e) configuration register write ack by tcn75 pointer byte ack by tcn75 stop cond by master configuration byte 000000 d1 d0 0 00 d4 d2 d3 d1 d0 1 a2 a1 a0 r/w 00 1 91 99
tcn75 ds21490c-page 14 ? 2006 microchip technology inc. 6.0 packaging information 6.1 package marking information package marking data not available at this time. 6.2 taping form component taping orientation for 8-pin msop devices package carrier width (w) pitch (p) part per full reel reel size 8-pin msop 12 mm 8 mm 2500 13 in carrier tape, number of components per reel and reel size pin 1 user direction of feed standard reel component orientation for 713 suffix device w p component taping orientation for 8-pin soic (narrow) devices package carrier width (w) pitch (p) part per full reel reel size 8-pin soic (n) 12 mm 8 mm 2500 13 in carrier tape, number of components per reel and reel size standard reel component orientation for 713 suffix device pin1 user direction of feed p w
? 2006 microchip technology inc. ds21490c-page 15 tcn75 6.3 package dimensions 8-pin msop .122 (3.10) .114 (2.90) .122 (3.10) .114 (2.90) .043 (1.10) max. .006 (0.15) .002 (0.05) .016 (0.40) .010 (0.25) .197 (5.00) .189 (4.80) .008 (0.20) .005 (0.13) .028 (0.70) .016 (0.40) 6 max. .026 (0.65) typ. pin 1 dimensions: inches (mm) .050 (1.27) typ. 8 max. pin 1 .244 (6.20) .228 (5.79) .157 (3.99) .150 (3.81) .197 (5.00) .189 (4.80) .020 (0.51) .013 (0.33) .010 (0.25) .004 (0.10) .069 (1.75) .053 (1.35) .010 (0.25) .007 (0.18) .050 (1.27) .016 (0.40) 8-pin soic dimensions: inches (mm)
tcn75 ds21490c-page 16 ? 2006 microchip technology inc. notes:
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tcn75 ds21490c-page 18 ? 2006 microchip technology inc. reader response it is our intention to provide you with the best documentation possible to ensure successful use of your microchip prod- uct. if you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please fax your comments to the technical publications manager at (480) 792-4150. please list the following information, and use this outline to provide us with your comments about this document. to : technical publications manager re: reader response total pages sent ________ from: name company address city / state / zip / country telephone: (_______) _________ - _________ application (optional): would you like a reply? y n device: literature number: questions: fax: (______) _________ - _________ ds21490c tcn75 1. what are the best features of this document? 2. how does this document meet your hardware and software development needs? 3. do you find the organization of this document easy to follow? if not, why? 4. what additions to the document do you think would enhance the structure and subject? 5. what deletions from the document could be made without affecting the overall usefulness? 6. is there any incorrect or misleading information (what and where)? 7. how would you improve this document?
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